This invention relates to an information processing system for use in processing a vector instruction in a pipeline fashion in addition to a scalar instruction.
A conventional information processing system of the type described comprises a processor section which cooperates with a memory section under control of a memory control section to process a sequence of instructions classified into scalar and vector instructions. In order to process such scalar and vector instructions, the processor comprises a scalar processing section for processing the scalar instructions together with scalar data signals and a vector processing section for processing the vector instructions together with vector data signals.
Furthermore, consideration has been made about effectively and quickly processing the vector instructions in a pipeline fashion. To this end, a proposal has been offered as regards an information processing system which comprises a plurality of vector pipeline sets in a vector processing section and which may be called a parallel-pipeline system hereinunder. In this event, each of the vector pipeline sets includes a plurality of vector registers for storing vector data signals and a plurality of pipeline calculators for carrying out vector calculations of the vector data signals stored in the vector registers. The parallel-pipeline system should comprise a vector processor unit for controlling the plurality of the vector pipeline sets by decoding the vector instructions and by delivering a control signal, namely, vector instruction information signals to the vector pipeline sets in response to each vector instruction.
More specifically, the vector processor unit is operable in response to each of the vector instructions to distribute a sequence of vector data signals or elements to the vector registers located within the plurality of the vector pipeline sets and to load the vector registers with the vector data signals. Such vector data signals are processed in parallel to one another to execute a specific one of the vector calculations in each vector pipeline set to which the vector data signals are distributed. In other words, the vector data signals or elements are equally distributed to the respective vector pipeline sets so as to always operate them in parallel.
With this structure, when the vector data signals or elements are very large in number, all the vector pipeline sets are effectively and equally operated or used for the specific vector calculation. However, when the number of the vector data elements is comparatively small for the specific vector calculation and when different vector calculations must be successively carried out after the specific vector calculation, idle or unused time intervals very often happen in each of the vector pipelines. This results in a reduction of utilization efficiency in hardware.